Generally, in synchronous serial communications, transmitted and received bits are synchronized to a common clock signal. When data is transferred between a transmitter and a receiver, a data valid window wide enough and occurring at a predictable time is used in order to ensure proper data capture by the receiver. The timing of the data valid window depends on the round-trip delay of the clock and data. This round-trip delay depends on the process, temperature, operating voltage conditions, and of the printed circuit board (PCB) layout. Although the process and PCB layout are stable, the temperature and operating voltage can vary over time. For example, the variation of the operating voltage has a much shorter time constant than that of the temperature.
One method for predicting the timing of the data valid window is a data learning pattern, such as the preamble pattern disclosed by U.S. Pat. No. 8,417,874, which is hereby incorporated herein by reference in its entirety. Using DLP, the transmitter sends a pre-determined data learning pattern at the beginning of each data frame. For each data line, the receiver can calibrate the data capture point so that it is in the center of the data valid window. However, for long data frames, there is the possibility that the timing of the data valid window drifts due to changes in the operating conditions, e.g. the operation voltage. In some cases, this drift may lead to a situation where the data cannot be reliably captured anymore, causing corruption of received data. Even with the use of DLP, the data corruption may not be detected within the data frame.